View WV3EG6437S403D4SG_1337000.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

White Electronic Designs
WV3EG6437S-D4
ADVANCED*
256MB - 2x16Mx64 DDR SDRAM SO-DIMM, UNBUFFERED
FEATURES
Unbuffered Double-data-rate architecture DDR300 and DDR400 * JEDEC design specifications Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2.5, 3 Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh, (8K/64ms Refresh) Serial presence detect with EEPROM Dual Rank Power Supply: VCC = VCC: 2.5V 0.2V (DDR300) VCC = VCCQ: 2.6V 0.1V (DDR400) JEDEC standard 200 pin SO-DIMM package * Package height options: D4: 31.75mm (1.25") TYP
NOTE: Consult factory for availability of: * RoHS compliant products * Vendor source control options * Industrial temperature option * This product is under development, is not qualified or characterized and is subject to change without notice.
DESCRIPTION
The WV3EG6437S is a 2x16Mx64 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM components. The module consists of eight 16Mx16 DDR SDRAMs in 66 pin TSOP package mounted on a 200 Pin FR4 substrate.
OPERATING FREQUENCIES
DDR400@CL=3 Clock Speed CL-tRCD-tRP 200MHz 3-3-3 DDR333@CL=2.5 166MHz 2.5-3-3
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June 2006 Rev. 0 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
PIN CONFIGURATIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol VREF VREF VSS VSS DQ0 DQ4 DQ1 DQ5 VCC VCC DQS0 DM0 DQ2 DQ6 VSS VSS DQ3 DQ7 DQ8 DQ12 VCC VCC DQ9 DQ13 DQS1 DM1 VSS VSS DQ10 DQ14 DQ11 DQ15 VCC VCC CK0 VCC CK0# VSS VSS VSS DQ16 DQ20 DQ17 DQ21 VCC VCC DQS2 DM2 DQ18 DQ22 Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol VSS VSS DQ19 DQ23 DQ24 DQ28 VCC VCC DQ25 DQ29 DQS3 DM3 VSS VSS DQ26 DQ30 DQ27 DQ31 VCC VCC NC NC NC NC VSS VSS NC NC NC NC VCC VCC NC NC NC NC VSS VSS NC VSS NC VCC VCC VCC CKE1 CKE0 NC NC A12 A11 Pin 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Symbol A9 A8 VSS VSS A7 A6 A5 A4 A3 A2 A1 A0 VCC VCC A10 BA1 BA0 RAS# WE# CAS# CS0# CS1# NC NC VSS VSS DQ32 DQ36 DQ33 DQ37 VCC VCC DQS4 DM4 DQ34 DQ38 VSS VSS DQ35 DQ39 DQ40 DQ44 VCC VCC DQ41 DQ45 DQS5 DM5 VSS VSS Pin 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Symbol DQ42 DQ46 DQ43 DQ47 VCC VCC VCC CK1# VSS CK1 VSS VSS DQ48 DQ52 DQ49 DQ53 VCC VCC DQS6 DM6 DQ50 DQ54 VSS VSS DQ51 DQ55 DQ56 DQ60 VCC VCC DQ57 DQ61 DQS7 DM7 VSS VSS DQ58 DQ62 DQ59 DQ63 VCC VCC SDA SA0 SCL SA1 VCCSPD SA2 NC NC
WV3EG6437S-D4
ADVANCED
PIN NAMES
A0 - A12 BA0-BA1 DQ0-DQ63 DQS0-DQS7 CK0, CK1 CK0#, CK1# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# DM0-DM7 VCC VSS VREF VCCSPD SDA SCL SA0-SA2 NC Address input Bank Select Address Data Input/Output Data Strobe Input/Output Clock Inputs Clock Enable Inputs Chip select Inputs Row Address Strobe Column Address Strobe Write Enable Data Mask Power Supply Ground Reference Power Supply Serial EEPROM Power Supply Serial data I/O SPD clock input SPD address No Connect
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June 2006 Rev. 0 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
WV3EG6437S-D4
ADVANCED
CS1# CS0# DQS0 DM0
LDQS LDM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQS UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS# LDQS LDM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQS UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS#
DQS1 DM1
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
LDQS LDM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQS UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
CS#
LDQS LDM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQS UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
CS#
DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
LDQS LDM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQS UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
CS#
LDQS LDM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQS UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
CS#
DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
LDQS LDM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQS UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
CS#
LDQS LDM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQS UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
CS#
DDR SDRAMs DDR SDRAMs Clock Wiring Clock Input CK0/CK0# CK1/CK1# 4 SDRAMs 4 SDRAMs CK0/1 CK0/1# DDR SDRAMs DDR SDRAMs R=120
BA0, BA1 A0-A12 RAS# CAS# CKE0 WE# CKE1
BA0, BA1: DDR SDRAMs A0-A12: DDR SDRAMs RAS#: DDR SDRAMs CAS#: DDR SDRAMs CKE0: DDR SDRAMs WE#: DDR SDRAMs CKE1: DDR SDRAMs
SCL
SERIAL PD SDA WP A0 A1 A2 SA0 SA1 SA2
VCCSPD VCC VREF VSS
SPD DDR SDRAMs DDR SDRAMs DDR SDRAMs
Note: All resistor values are 22 ohms 5% unless otherwise specified.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June 2006 Rev. 0 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Operating Temperature Power Dissipation Short Circuit Current
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
WV3EG6437S-D4
ADVANCED
Symbol VIN, VOUT VCC, VCCQ TSTG TA PD IOS
Value -0.5 to 3.6 -0.5 to 3.6 -55 to +150 0 - 70 8 50
Units V V C C W mA
DC CHARACTERISTICS
0C TA 70C Parameter Supply voltage DDR333 I/O Supply voltage DDR333 Supply Voltage DDR400 I/O Supply Voltage DDR400 I/O Reference voltage I/O Termination voltage Input logic high voltage Input logic low voltage Input voltage level, CK and CK# Input differential voltage, CK and CK# Input crossing point voltage, CK and CK# Addr, CAS#, RAS#, WE# Input leakage current CS#, CKE CK, CK# DM Output leackage current Output high surrent (normal strength) VOUT = VTT + 0.84V Output high surrent (normal strength) VOUT = VTT - 0.84V Output high surrent (half strength) VOUT = VTT + 0.45V Output high surrent (half strength) VOUT = VTT - 0.45V DQ, DQS IOZ IOH IOL IOH IOL II Symbol VCC VCCQ VCC VCCQ VREF VTT VIH(DC) VIL(DC) VIn(DC) VID(DC) VIX(DC) Min 2.3 2.3 2.5 2.5 0.49 + VCC VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.36 0.3 -16 -8 -8 -4 -10 -16.8 16.8 -9 9 Max 2.7 2.7 2.7 2.7 0.51 + VCC VREF + 0.04 VCC + 0.30 VREF - 0.15 VCC + 0.30 VCC + 0.60 VCC + 0.60 16 8 8 4 10 Unit V V V V V V V V V V V A A A A A mA mA mA mA
Notes: 1. VREF is expected to equal 0.5*VCCQ of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-2 percent of the DC value. 2. VTT in sot applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 3. VID is the magnitude of the difference between the input level on CK and the input level of CK#. 4. VCCQ of all IC's are ited to VCC.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June 2006 Rev. 0 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
AC OPERATING CONDITIONS
All voltages referenced to VSS Parameter Input High (Logic1) Voltage Input Low (Logic0) Voltage Input Differential Voltage, CK and CK# input Input Crossing Point Voltage, CK and CK# input
Notes:
WV3EG6437S-D4
ADVANCED
Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC)
Min. VREF + 0.31
Max. VREF - 0.31
Units V V V V
Notes 1 1
0.7 0.5*VCC - 0.2
VCCQ + 0.6 0.5*VCC + 0.2
1.
VIH overshoot: VIN = VCC + 1.5V for a pulse width 3ns and the pulse can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL = -1.5V for a pulse width 3ns and the pulse can not be greater than 1/3 of the cycle rate.
INPUT/OUTPUT CAPACITANCE
TA = 25C, f = 100MHz Parameter Input Capacitance (A0~A12, BA0~BA1, RAS#, CAS#, WE#) Input Capacitance (CKE0, CKE1) Input Capacitance (CS0#, CS1#) Input Capacitance CK, CK0#, CK1, CK1#) Input Capacitance (DM0 ~ DM7), (DQS0 ~ DQS7) Input Capacitance (DQ0 ~ DQ63) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 COUT1 Min 20 12 12 12 12 12 Max 28 16 16 16 14 14 Units pF pF pF pF pF pF
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June 2006 Rev. 0 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
ICC SPECIFICATIONS AND TEST CONDITIONS
Parameter Symbol Conditions One device bank; Active - Precharge; tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device bank; Active-Read-Precharge; Burst = 2; tRC=tRC(MIN);tCK=tCK(MIN) ; Iout = 0mA; Address and control inputs changing once per clock cycle. All device banks idle; Power- down mode; tCK=tCK(MIN); CKE=(low) CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high; Address and other control inputs changing once per clock cycle. Vin = Vref for DQ, DQS and DM. One device bank active; Power-down mode; tCK(MIN); CKE=(low) CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continous burst; One device bank active;Address and control inputs changing once per clock cycle; tCK=tCK(MIN); Iout = 0mA.
WV3EG6437S-D4
ADVANCED
DDR403 @CL=3 Max 456 616 32 240 400 520 736 736 1,600 24 1,416
DDR333 @CL=2.5 Max 372 512 24 240 280 440 652 652 1,440 24 1,332
Units
Operating Current Operating Current Precharge PowerDown Standby Current Idle Standby Current Active Power-Down Standby Current Active Standby Current Operating Current Operating Current Auto Refresh Current Self Refresh Current Operating Current
ICC0* ICC1* ICC2P** ICC2F** ICC3P** ICC3N** ICC4R*
mA mA mA mA mA mA mA mA mA mA mA
Burst = 2; Writes; Continous burst; One device bank active; Address and ICC4W** control inputs changing once per clock cycle; tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per clock cycle. ICC5** ICC6** ICC7* tRC=tRC(MIN) CKE 0.2V Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change only during Active Read or Write commands.
Note: ICC specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different. * Value calculated as one module rank in this operation condition, and all other module ranks in ICC2P (CKE LOW) mode. ** Value calculated reflects all module ranks in the operating condition.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June 2006 Rev. 0 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WV3EG6437S-D4
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (1 V/ns) Address and control input setup time (1 V/ns) Address and control input hold time (0.5 V/ns) Address and control input setup time (0.5 V/ns) Address and Control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time CL = 3 CL = 2.5 SYMBOL tAC tCH tCL tCK (3) tCK (2.5) tDH tDS tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ tIHF tISF tIHS tISS tIPW tMRD tQH tQHS tRAS tRAP tRC tRFC tRCD tRP tRPRE tRPST tRRD tWPRE tWPRES MIN -0.65 0.45 0.45 5 0.40 0.40 1.75 -0.55 0.35 0.35 403 MAX +0.65 0.55 0.55 10 MIN -0.7 0.45 0.45 6 0.40 0.40 1.75 -0.60 0.35 0.35 335 MAX +0.7 0.55 0.55 12 UNITS ns tCK tCK ns ns ns ns ns ns tCK tCK ns tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCK tCK ns tCK ns
+0.65
+0.60
0.40 0.72 1.28 0.20 0.20 tCH(MIN) or tCL(MIN) +0.65 -0.65 0.60 0.60 0.70 0.70 2.20 10 tHP - tQHS 0.50 40 70K 15 55 70 15 15 0.90 1.10 0.40 0.60 10 0.25 0
0.45 0.75 1.25 0.20 0.20 tCH(MIN) or (MIN) +0.70 -0.70 0.75 0.75 0.80 0.75 2.20 10 tHP - tQHS 0.55 42 70K 18 60 72 18 18 0.9 1.10 0.4 0.60 12 0.25 0
Note: AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. Continued on next page
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June 2006 Rev. 0 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WV3EG6437S-D4
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued)
AC CHARACTERISTICS PARAMETER DQS write postamble Write recovery time Internal WRITE to READ command delay Average periodic refresh interval Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command Auto precharge write recovery + precharge time SYMBOL tWPST tWR tWTR tREFI tXSNR tXSRD tRAL MIN 0.40 15 2 7.80 75 200 tWR/tCK
+tRP/tCK
403 MAX 0.60 MIN 0.40 15 1
355 MAX 0.60 UNITS tCK ns tCK 7.80 75 200 tWR/tCK
+tRP/tCK
s ns tCK tCK
Note: AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June 2006 Rev. 0 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
ORDERING INFORMATION FOR D4
Part Number WV3EG6437S403D4xxG WV3EG6437S335D4xxG Speed/Data Rate Frequency 200MHz/400Mbps, CL=3 166MHz/333Mbps, CL=2.5
WV3EG6437S-D4
ADVANCED
Height* 31.75 (1.25") TYP 31.75 (1.25") TYP
NOTES: * Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR D4
FRONT VIEW
67.75 (2.667) 67.45 (2.656) 3.81 (0.150) MAX
4.10(0.161) (2X) 3.90(0.154) 1.80 (0.071) (2X) 31.90 (1.256) 31.60 (1.244) 20.00 (0.787) TYP
6.00 (0.240) 2.55 (0.100) 1.80 (0.071) 2.15 (0.085) 1.00 (0.039) TYP 0.45 (0.018) TYP 2.504 (63.60) TYP 0.60 (0.024) TYP 1.10 (0.043) 0.90 (0.035)
PIN 1
PIN 199
BACK VIEW
4.06 (0.160) 1.50 (0.059) 4.2 (0.165) TYP 47.40 (1.866) TYP 11.40 (0.449) TYP
PIN 200
PIN 2
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June 2006 Rev. 0 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
PART NUMBERING GUIDE
WV3EG6437S-D4
ADVANCED
WV 3 E G 64 37 S xxx D4 x x G
WEDC MEMORY DDR GOLD BUS WIDTH 2x16M 2.5V SPEED (Mb/s) PACKAGE 200 PIN INDUSTRIAL TEMP OPTION (For commercial leave "blank" for industrial add "I" COMPONENT VENDOR NAME (M = Micron) (S = Samsung) (N = Nanya) G = RoHS COMPLIANT
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June 2006 Rev. 0 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
256MB - 32Mx64, DDR SDRAM UNBUFFERED DRAM DIE OPTIONS: * SAMSUNG: H-Die (K4H561638H-UCB3) RoHS * MICRON: T26A: F-Die
WV3EG6437S-D4
ADVANCED
Revision History Rev #
Rev 0
History
Created
Release Date
June 2006
Status
Advanced
White Electronic Designs Corp. reserves the right to change products or specifications without notice. June 2006 Rev. 0 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

▲Up To Search▲

Price & Availability of WV3EG6437S403D4SG

	To Download WV3EG6437S403D4SG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .